Static random access memory (SRAM) is a type of volatile semiconductor memory that stores data bits using bistable circuitry that does not need refreshing. A cell of a memory such as SRAM may be referred to as a bit cell because it stores one bit of information, represented by the logic state of two cross coupled inverters. Memory arrays include multiple bit cells arranged in rows and columns. Each bit cell in a memory array typically includes connections to a power supply voltage and to a reference (e.g., ground) voltage. Logic signals on bit lines control reading from and writing to a bit cell, with a word line controlling connections of the bit lines to the inverters, which otherwise float. A word line may be coupled to the bit cells in a row of a memory array, with different word lines provided for different rows. A pair of bit lines may be coupled to each column of bit cells. For a read operation at a bit cell, the corresponding bit lines may be precharged high (e.g., to a logical high value ‘1’), and the corresponding word line may be asserted. The resulting values at the bit lines may correspond to the logical value of the bit of information stored at the bit cell. To write a ‘1’ into a bit cell, one of the corresponding bit lines, which may be denoted BL (which may stand for “bit line”), may be set to ‘1’ and the other bit line, which may be denoted BLB (which may stand for “bit line bar”), may be set to ‘0’, and the word line may be asserted. To write a logical low value, BL and BLB may instead be set to ‘0’ and ‘1’, respectively, and the word line may be asserted. The pair of bit lines BL, BLB may be referred to as a pair of complementary bit lines. It is understood nonetheless that the values at BL and BLB need not be logical complements of one another, e.g., as in the read operation described above, where BL and BLB are both set to ‘1’.
To improve memory access performance (e.g., write performance), dual rail power supply techniques have been used previously. In a dual rail power supply approach, a power supply voltage CVDD (which may stand for “cell VDD”) may be provided to bit cells. CVDD may have a first voltage level (e.g., a power supply voltage VDD) in certain situations, e.g., for a first type of memory operation, and may have a second voltage level in other situations, e.g., for a second type of memory operation.